About the Role
You will design SoC power-management hardware, thermal and current control loops, and clock and reset architecture. You will implement power states and DVFS, work on voltage droop and power delivery behavior, correlate power estimates from RTL through silicon, and define firmware and software interfaces for power telemetry and policy.
Requirements
•Knowledge of average power, peak current, thermal behavior, and voltage droop
•Experience designing power-management hardware, digital power meters, throttlers, or thermal and current control loops
•Knowledge of di/dt, IR drop, power-delivery networks, and timing margin
•Experience with clock and reset architecture, clock gating, PLL management, and reset sequencing
•Knowledge of Verilog or SystemVerilog and RTL design methodology
•Experience with RTL-to-gate-level power estimation and analysis
•Debugging and problem-solving skills across hardware and software
•Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or a related field
Responsibilities
•Design SoC power-management hardware, including digital power meters, activity monitors, and throttlers
•Design hardware and software control loops around temperature sensors
•Design controls for activity, average power, and instantaneous di/dt limits
•Work on voltage droop behavior, power delivery, and adaptive clocking response
•Own clock and reset architecture, including clock gating, PLL management, and reset sequencing
•Define and implement DVFS, power domains, retention, and low-power flows
•Correlate power estimates across RTL, emulation, and silicon and build power and thermal telemetry
•Define power and thermal management interfaces and policies with firmware and software teams
Benefits
•Equity compensation
•Medical coverage
•Dental coverage
•Vision coverage
•Paid time off
•Flexible work arrangements
