Velaura AI

Power Management Architect (Physical AI)

In short

This role owns the power architecture for Physical AI SoCs, from early architecture through tape-out and production, covering power domains, DVFS strategies, power delivery networks, and power-management controls. The company is building Physical AI SoCs and needs someone to model power budgets, drive PPA trade-offs, and validate low-power intent through silicon bring-up. It requires 8+ years of experience in power management, mixed-signal, or SoC architecture, along with expertise in UPF/CPF methodology and power modeling across the SoC design flow. The role also involves technical leadership and mentoring engineers, and is onsite in India.

About the Role
You will own the power architecture for Physical AI SoCs from early architecture through tape-out and production. You will define power domains, DVFS strategies, power states, delivery networks, and power-management controls. You will model power budgets, drive PPA trade-offs, validate low-power intent, and establish power architecture standards and review practices.
Requirements
•8+ years of experience in power management, mixed-signal, or SoC architecture
•Expertise in low-power design techniques, including power domains, DVFS, clock and power gating, adaptive voltage scaling, retention, and power-state management
•Understanding of power delivery networks, PMICs, voltage regulation, and power, thermal, and package constraints
•Experience with power intent and low-power methodology, including UPF or CPF
•Experience with power modeling and analysis across the SoC design flow
•Experience defining and validating power-management policies across silicon design, firmware, and platform software
•Bachelor's or advanced degree in Electrical or Computer Engineering or a related field, or equivalent practical experience
•Written and verbal communication
•Technical leadership
•Mentoring
Responsibilities
•Own the SoC power architecture, including power domains, DVFS strategy, power states, and power delivery networks
•Define dynamic and static power-management techniques, including clock and power gating, adaptive voltage scaling, body biasing, and retention strategies
•Establish power and energy budgets and drive power, performance, and area trade-offs
•Architect on-die power-management controls, including PMIC interfaces, controllers, sensors, telemetry, and software policies
•Embed power intent into the design flow and validate it through implementation and silicon bring-up
•Define power and thermal management strategies, including thermal throttling, energy-aware scheduling, and safe operating limits
•Establish power architecture standards, modeling methodology, and review practices
•Mentor engineers
Benefits
•Equity compensation
•Medical coverage
•Dental coverage
•Vision coverage
•Paid time off
•Flexible work arrangements

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