About the Role
You will lead RTL development for key SoC areas and translate system requirements into robust microarchitectures. You will guide hardware and software co-design, review architecture and RTL, optimize for performance, power, and area, establish engineering methods, and mentor RTL engineers through silicon bring-up.
Requirements
•RTL design experience in complex SoCs, CPUs, GPUs, AI accelerators, networking devices, or related systems
•Understanding of digital design fundamentals and microarchitecture
•Experience with Verilog, SystemVerilog, and modern RTL development methodologies
•Knowledge of memory systems, interconnect fabrics, cache hierarchies, and system-level data movement
•Experience balancing performance, power, area, and design complexity
•Ability to drive technical projects from concept through silicon bring-up
•Experience with hardware and software co-design and full-stack performance optimization
Responsibilities
•Lead RTL development across key SoC areas
•Translate system requirements into robust microarchitectures with architects
•Drive hardware and software co-design across AI workloads, memory systems, runtime software, and system architecture
•Define programming models, execution flows, memory hierarchies, and performance-critical interfaces with software teams
•Drive design decisions across compute, memory, interconnect, control, and system infrastructure
•Develop power-efficient and scalable RTL implementations
•Conduct architecture and RTL reviews to meet performance, power, and area goals
•Collaborate with performance modeling, verification, physical design, and software teams
•Establish engineering processes and design methodologies
•Mentor and develop RTL engineers
Benefits
•Equity compensation
•Medical coverage
•Dental coverage
•Vision coverage
•Paid time off
•Flexible work arrangements
