Senior Engineer CAD Pre-Silicon Front End
Company: Velaura AI, Inc.
Conditions: Salary: 200K - 300K
About the Role
You will own RTL, register-generation, design-verification, emulation, and FPGA-prototyping flows. You will build AI-assisted tooling, maintain reliable engineering workflows, improve productivity, and partner on DFT and physical-design handoff readiness.
Requirements
•Eight or more years in design verification, design, or CAD engineering
•SystemVerilog and RTL fluency
•Experience building and running simulation and regression flows
•Python skills
•Knowledge of Synopsys, Cadence, or Siemens EDA tools
•Knowledge of Linux administration and distributed compute systems such as LSF or Slurm
•Familiarity with databases and dashboarding tools such as Grafana
•Experience supporting live engineering flows
Responsibilities
•Own RTL design flows including build, lint, CDC, and formal checks
•Own register generation and generator-driven interface and integration flows
•Own design-verification flows including testbench builds, regressions, and coverage collection
•Own emulation and FPGA-prototyping builds and bring-up
•Build and deploy AI-assisted tooling for design and verification workflows
•Maintain tools, manage versions, and resolve maintenance requests
•Measure and improve design and verification productivity
•Partner on DFT and physical-design handoff readiness
Benefits
•Equity compensation
•Medical coverage
•Dental coverage
•Vision coverage
•Paid time off
•Flexible work arrangements
