SoC Design Verification Engineer
Company: Velaura AI, Inc.
Salary: 200K – 300K
About the Role
You will plan and execute system-level SoC verification, build simulation environments, and verify boot, security, clock, reset, low-power, IO, and memory behavior. You will run CDC and RDC analysis, assess performance, and support coverage closure and tape-out readiness.
Requirements
•Ten or more years in design verification with significant SoC-level experience
•Experience with multiple SoC verification projects through sign-off and tape-out
•Experience with SystemVerilog, UVM, C, C++, and coverage-driven verification
•Experience managing simulation flows on ARM or RISC-V SoCs
•Knowledge of PCIe and LPDDR5 or LPDDR6
•Experience verifying boot sequences, root of trust, clock and reset topology, and low-power behavior
•Experience with CDC, RDC, low-power verification tools, and UPF-based flows
Responsibilities
•Drive verification planning and execution for assigned SoC areas
•Build and maintain SoC-level simulation environments and flows
•Verify boot flows, root of trust, security transitions, and firmware handoff
•Verify clock and reset topology, power domains, and low-power behavior
•Verify IO and memory subsystem integration including PCIe and LPDDR
•Run CDC and RDC analysis and close findings
•Verify latency, bandwidth, and QoS under representative workloads
•Support sign-off criteria, coverage closure, and tape-out readiness
Benefits
•Equity compensation
•Medical coverage
•Dental coverage
•Vision coverage
•Paid time off
•Flexible work arrangements
