Velaura AI

Design Verification Engineer CPU

In short

This role owns design verification for functional domains of a custom CPU, covering test planning through coverage closure. The company builds UVM/SystemVerilog verification environments, instruction-level stimulus, and compares results against a golden instruction set simulator, while verifying cache behavior, memory ordering, coherence, and exceptions. It demands 8+ years verifying high-performance CPUs or complex digital designs, strong SystemVerilog/UVM/C/C++ skills, and supports emulation, FPGA prototyping, and pre-silicon software bring-up. The position is onsite in India.

About the Role
You will own verification for functional domains of a custom CPU, from test planning through coverage closure. You will build verification environments, develop instruction-level stimulus, validate CPU behavior and performance, run regressions, and support emulation, FPGA prototyping, and software bring-up.
Requirements
•8 or more years verifying high-performance CPUs or complex digital designs
•Computer architecture and microarchitecture
•SystemVerilog
•UVM
•C
•C++
•Assertions
•Coverage-driven verification
•Test planning
•Portable testbenches
•Transactors
•Hardware/software debugging
Responsibilities
•Own verification of CPU fetch, decode, load-store, and cache units
•Create detailed test and coverage plans with CPU and SoC architects
•Build verification environments using SystemVerilog, UVM, C, and C++
•Develop instruction-level stimulus and compare results with a golden instruction set simulator
•Verify memory ordering, coherence, exceptions, and privilege behavior
•Verify latency, bandwidth, and cache behavior
•Execute regressions and track bug and coverage metrics
•Support emulation, FPGA prototyping, and pre-silicon software bring-up
•Drive root-cause analysis across hardware and software boundaries
Benefits
•Competitive equity compensation
•Medical coverage
•Dental coverage
•Vision coverage
•Paid time off
•Flexible work arrangements

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