Job Description
In this role you will be responsible for enabling EDA vendor tools for RC Extraction (StarRC, Quantus, xACT, etc), and EM tools for high-frequency analysis on Intel's process technologies. Candidate will work with technology specification owners and validation teams in a coordinated fashion to ensure a high-quality solution. Interaction with EDA vendors is expected for new feature enablement.
Intel Foundry Business Group focuses on providing world-class manufacturing capabilities, innovative process technologies, and customized solutions to our global customers. As part of the Intel Foundry organization, you will join a team dedicated to enabling customers' success by bringing their ideas to life through advanced semiconductor solutions.
Well qualified candidates should possess the following behavioral traits:
•Excellent communication and presentation skills for technical and non-technical audiences
•High motivation and enthusiasm for self-directed, hands-on work
•Creativity and flexibility to thrive under changing priorities and evolving program needs
•Strong analytical thinking and problem-solving capabilities
•Collaborative mindset with ability to work effectively across diverse teams
•Adaptability to work in a fast-paced, innovative environment
You will be working at the intersection of cutting-edge semiconductor technology development and creating solutions that push the boundaries of what's possible in computing.
Qualifications
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.
Minimum Qualifications
Candidate must possess BS degree with 4+ years of relevant experience, or MS degree with 3+ years of experience or PhD degree in EE/ECE or related field.
2+ years of experience in one of the following two skill sets:
Skill set 1:
•RC extraction flow enablement such as StarRC or Quantus or SMNS-xACT
•Scripting in Perl, or Python or TCL
Skill Set 2:
•Interconnect Stack development for EDA tools such as ITF, ICT, MIPT, EM stack (Keysight-momentum) or equivalent.
•Scripting in Perl, or Python or TCL
Preferred Qualifications
2+ years of experience in the following:
•DRC/LVS runset development or validation such as Calibre, Pegasus or ICV.
•Customer Support and debugging in RC extraction.
•High frequency tools such as Keysight-momentum, Ansys, Cadence-EMX.
•Experience with JIRA, GIT.
•Proficiency with CMOS process technology.
Desired experience
•Electromagnetic (EM) modeling and simulation tools and their application to signal integrity/crosstalk analysis for high-speed/high-density on chip/on package interconnect.
•Working with EDA tool vendors to enable customized solutions.
Compensation varies depending on number of matching skills, geographical location, and years of experience.
Job Type
Experienced Hire
Shift
Shift 1 (United States of America)
Primary Location
US, Texas, Austin
Additional Locations
US, California, Folsom, US, California, Santa Clara, US, Oregon, Hillsboro
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.
