About the Role
Join our FPGA engineering team and help deliver high-performance digital logic, CPLD/CFPGA modules, and hardware acceleration platforms for our next-generation firewalls. You will own FPGA design from architecture and specification through RTL, timing closure, synthesis, and lab bring-up, collaborating closely with cross-functional software, hardware, and verification teams.
What You'll Do
•Write comprehensive micro-architecture and functional specifications for FPGA, CFPGA, and CPLD designs.
•Design high-quality SystemVerilog/Verilog RTL targeted for advanced FPGA architectures (AMD/Xilinx, Altera) meeting strict timing, power targets.
•Synthesize & Implement designs using Vivado, Quartus, and Synopsys tools, achieving multi-clock timing closure and resource optimization.
•Prototype & Validate ASIC designs on FPGA platforms, executing lab bring-up, in-system debugging, and hardware validation.
•Collaborate with software teams to define interfaces, review memory map structures, and integrate complex IP blocks (PCIe, Ethernet, DMA, DDR/LPDDR).
•Innovate: pilot AI-driven design or verification flows that cut schedule risk.
Qualifications
Required Qualifications
•BS in EE, CE, or CS (MSEE or equivalent military experience preferred).
•5+ years FPGA/CPLD development experience.
•Expert SystemVerilog and Verilog RTL development skills for FPGA and CPLD architectures and is familiar with simulation tools, such as: VCS, Questa, etc. for block level verification.
•Proven track record of FPGA synthesis, placement, routing, and static timing analysis (STA) closure across multi-clock domains.
•Scripting proficiency (Python, C/C++, Perl, bash or tcsh).
•Demonstrated strength in:
•Integrating and configuring high-speed IP cores (e.g., PCIe Gen4/5/6, DMA, Ethernet MAC/PHY, memory controllers).
•FPGA rapid prototyping, in-system logic debugging (ILA, SignalTap), and lab bring-up.
•Optimizing resource utilization (LUTs, FFs, BRAM/URAM, DSP blocks) and timing closure strategies.
•Analyzing timing, power, and area reports and driving fixes.
•Demonstrated proficiency or active experience integrating modern AI tools (e.g., LLM coding assistants, automated test generators, or ML-enhanced EDA features) into hardware design, scripting, or verification workflows.
•Excellent leadership, collaboration, and written/verbal communication.
Preferred / Nice-to-Have
•Experience with ASIC-to-FPGA prototyping flows and emulation environments.
•Hands-on experience with high-density FPGA platforms (AMD UltraScale+/Versa, Altera Agilex/Stratix).
•Formal verification techniques (e.g., VC Formal) applied to FPGA module verification.
•Networking experience (Ethernet packet processing) and CPLD/CFPGA board-management logic design.
Compensation
The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary is expected to be the annual range listed below. The offered compensation may also include restricted stock units and a bonus.
$156,400.00 - $253,000.00/yr
Immigration Sponsorship
This role is eligible for immigration sponsorship.
