NVIDIA

Senior Physical Design Methodology Engineer, PPA Improvement Technology Scaling

In short

Senior Physical Design Methodology Engineer role at NVIDIA, developing physical design methodologies and PPA (power, performance, area) improvement techniques for GPUs, CPUs and SOCs. The role covers floorplanning, power/clock distribution, place and route, timing closure, and automation scripting for new technology nodes. Requires an MS in EE/CE or equivalent, at least 5 years of physical design experience, strong knowledge of EDA tools, and proficiency in Perl, Python and C++. Based in Santa Clara, CA, with a base salary range of 168,000-310,500 USD depending on level.

About the Role
NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer(s) - PPA Improvement Technology Scaling to join our outstanding Methodology team. Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
•Developing physical design methodologies for implementation of graphics processors and SOCs.
•Key responsibility includes developing unique and creative solutions to the state of the art physical design problems that are needed for NVIDIA chips.
•Participate in PPA experiments for testing and developing new technologies for CPUs/GPUs including running chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.
•Develop Automation to solve early design collaterals, for eg. developing scripts for analysis of new library cells, scripts for modifying design constraints for new technologies.
What we need to see:
•MS in Electrical or Computer Engineering (or equivalent experience)
•Minimum 5 years' experience in Physical Design Engineering
•Familiar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.
•Experience with Physical Design related to CPU designs is a plus
•Strong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
•Familiar with various process related design issues including Design for Yield and Manufacturability, EM and IR closure and thermal management.
•You'll need to have expertise and in-depth knowledge of industry standard EDA tools.
•Proficiency in programming and scripting languages, such as, Perl, Python, and C++.
Compensation
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 1, 2026. This posting is for an existing vacancy.
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