Job Description
Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations.
To support Intel Foundry strategy, we are looking for talents to join this exciting journey to drive design enablement in quality and reliability area on Intel leading technology nodes to build industry competitive design platform supporting customer design on Intel Si and package technologies. The general reliability design enablement includes PDK (Process Design Kits), TFM (tool/flow/methodology), Foundational IP (library, memory, analog IP) and DFR (Design for Reliability) to achieve best PPA (Power Performance Area) and reliability co-optimization.
This role will be responsible for but not limited to:
•Definition and generation of reliability related PDK design rule and collateral covering all reliability mechanism, QA (quality assurance) and benchmarking analysis.
•Drive industry EDA (Electronic Design Automation) tool and flow enablement in synergy with PDK development, work with internal partners and EDA vendors to deliver competitive TFM to support design reliability verification.
•Competitive analysis and benchmarking technology reliability, plan and deliver industry leading PDK, design rule, design collateral, TFM and IP ecosystem to enable internal and external customer design on Intel technology.
The Candidate Should Exhibit the Following Behavioral Traits:
•Excellent written and verbal communication and presentation skills.
•Passion for quality and attention for details and procedures, looking for opportunities to drive efficiency and innovations.
•Demonstrated capability to drive quality enhancements projects.
•Strong team player with proven ability to work in diverse multi-cultural environment.
•Must be flexible and adaptable to ensure program commitments are met on time in a dynamic work environment.
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
What we need to see (Minimum Qualifications):
•Bachelor's degree in electrical engineering, physics or a related field and 6+ years of relevant work experience or 4+ years of relevant experience and a master's degree, or a PhD degree with 2+ years of relevant experience.
•3+ years' experience in one of the following areas: PDK development, reliability tool and flow, design for reliability, Circuit, IP and SOC design reliability validation using PDK, EDA tool and flow development.
Preferred Qualifications:
•Master's degree in electrical engineering, physics, or related field, or Ph.D. degree in electrical engineering, physics, or related fields.
•Hands-on experience on PDK development and validation; knowledge and understanding of PDK fundamentals; reliability design rules and their implementation in PDK and TFM.
•Capability to use AI or program skills to write code, agent or script for design rule, techfile generation and quality assurance.
•Experience on PDK, EDA tool/flow development, design flow application and interaction with IP and SOC design validation and sign-off; design impact and risk assessment in related reliability area.
•Experience and knowledge on reliability verification and physics, such as aging including BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection), Electro-Migration, high voltage design, EOS (Electrical Over-Stress), ESD (Electrostatic Discharge).
•Experiences and skills in program management, stakeholder management, and strong communication skills.
Experience listed above would be obtained through a combination of school work/classes/research and/or relevant previous job and/or internship experiences.
Benefits
Intel's benefits package includes 14 paid holidays per calendar year, three weeks of paid vacation, and four-week paid sabbatical every four years of employment. Intel also offers employees five bonuses per year dependent on overall company and personal performance, and an employee stock purchase program. The total compensation package consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
Job Type: Experienced Hire
Shift: Shift 1 (United States of America)
Primary Location: US, Oregon, Hillsboro
Additional Locations: US, Arizona, Phoenix; US, California, Folsom; US, California, Santa Clara
Annual Salary Range for jobs which could be performed in the US: $173,660.00–284,580.00 USD. The range displayed reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
Work Model: This role is eligible for Intel's hybrid work model, allowing employees to split their time between working on-site at their assigned Intel site and off-site.
