Ciena

Principal Digital Verification Engineer

In short

Principal Digital Verification Engineer role at Ciena, working onsite in Rochester, NY on the WaveLogic optical transmission product family. The job involves driving digital verification strategies using SystemVerilog, UVM, SVA, simulation, and formal verification methods, including leading technical initiatives and acting as ASIC Verification Prime. Requires a Bachelor's degree in a relevant engineering/science field and 12+ years of digital verification experience. Salary range is $147,100–$234,900 per year.

Principal Digital Verification Engineer
The WaveLogic family of products is a key component of Ciena's optical fiber transmission solutions and contributes significantly to innovation in the telecommunications industry. This role provides the opportunity to drive verification strategies that help ensure the quality and performance of advanced optical networking technologies. Working alongside digital design engineers, verification engineers, and architects in our office in Rochester, NY, this position contributes to the successful delivery of WaveLogic products.
How you will make an impact:
•Analyze project architecture and functional requirements to collaborate with systems engineers and architects.
•Validate digital subsystems using simulation, formal verification, and coverage methodologies.
•Create, review, and optimize simulation environments, test scenarios, functional coverage plans, and formal verification test plans.
•Lead focused technical initiatives and mentor team members to achieve defined objectives when required.
•Estimate project schedules, track progress against approved plans to completion, and communicate status updates.
•Direct verification activities as an ASIC Verification Prime when assigned.
•Participate in architectural and design reviews to identify verification impacts and opportunities for improved coverage and schedule execution.
The must haves:
•Education: At least a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or other applicable scientific discipline.
•Experience: 12+ years using SystemVerilog, UVM, SVA, and simulators from major vendors in digital verification environments.
•Proven ability to determine comprehensive digital verification and coverage strategies.
•Ability to work independently and collaboratively within a team environment.
•Ability to debug complex technical problems using a methodical approach.
•Effective written and verbal English communication skills.
Nice to haves:
•Experience with application of formal verification methods.
•Experience with DSP and/or Forward Error Correction technologies.
•Experience using Jira for bug tracking and Git for source code management and revision tracking.
•Familiarity with Python, Make, bash, object-oriented programming, C, and C++.
Pay Range:
The annual salary range for this position is $147,100 - $234,900.
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time.

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