Samsung Electronics Polska

HW Verification Engineering Lead

In short

This role leads IP verification and pre-silicon validation for next-generation custom hardware IP covering camera, multimedia and display pipelines in smartphones, at Samsung's R&D operation in Bangalore. The team lead oversees the end-to-end IP lifecycle, validation methods for zero-bug silicon, and integration of complex sub-systems like PCIe, USB, DDR, ARM/RISC-V and MIPI. It demands deep expertise in System Verilog/UVM/OVM, digital design, CDC, synthesis, timing analysis and low power implementation, combined with people leadership and cross-functional coordination skills.

Position Summary
•Design, development & verification of H/W IP for camera, multimedia and display pipelines in smartphones
Role and Responsibilities
As the lead of IP Verification / Pre-Silicon Validation, you will head a team responsible for the verification of our next generation purpose specific custom HW IP. This critical role spans both in-house IP development as well as strategic evaluation, integration and validation of various other IP blocks. You will bridge the gap between technical execution and people mentorship, ensuring delivery, high quality, high performance and power-efficient hardware IPs that drive and differentiate our product line over competitors.
Skills and Qualifications
Key Responsibilities
Technical Execution and Delivery:
•Oversee the end-to-end IP lifecycle and advanced verification
•Ensure robust validation methods utilised to ensure zero-bug silicon
•Define and implement best-in-class engineering practices, checklists and design flows to maximise efficiency
Technical Competencies:
•Verification / Emulation
•Understanding of digital design principles, algorithm, design and architecture specifications
•Understanding of SystemC, C and Python programming
•Design direction in terms of performance, gate count and power for various digital designs
•Proficient in System Verilog/UVM/OVM
•FPGA IP/Custom ASIC prototyping and validation
•Developing scalable test benches in System Verilog and UVM
•Understanding of cameras / multimedia / display / NPU subsystems in detail
•Proven track record of integrating complex sub-systems (PCIe, USB, DDR, ARM/RISC-V Cores, MIPI etc)
•Design knowledge in Verilog, Linting, clock domain crossing (CDC), synthesis, Timing Analysis, Low Power Implementation (UPF/CPF, Clock Gating, Power Domain)
•Usage of AI tools, e.g., Claude, for IP development enhancement, KPI exploration
Key Leadership Trait:
•People developer
•Cross functional bridge
•Resource optimiser
•Decisive problem solver
•Influencer and navigator
Desired Qualification
Graduate / Post Graduate in Electrical / Electronic Engineering / VLSI Design / Microelectronics

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