NVIDIA is looking for a hands-on, execution-focused Technical Program Manager to drive the DFX programs of our groundbreaking chip designs from plan of record through production release. This role sits at the junction of chip design, manufacturing test, and product quality, and is accountable for getting our silicon test-ready, production-ready and released on schedule.
NVIDIA is seeking someone with a strong background in silicon bring-up and productization, with a focus on testability. You will own DFX program execution across the full lifecycle, from plan of record to production release, with particular emphasis on the post-silicon phases where test content, yield and quality come together for release. Your goal is to keep DFX deliverables on track to program milestones, surface risks early, and ensure smooth execution from first silicon through production ramp.
What you'll be doing:
•Work closely with DFX engineering managers and engineers, as well as cross-functional partners in silicon design, physical design, verification, post-silicon validation, test engineering, operations and software, to drive DFX execution across multiple concurrent programs.
•Own the integrated DFX execution schedule for assigned programs from plan of record through production release, tracking dependencies and deliverables against key milestones including tapeout, first silicon, bring-up, qualification and release
•Drive pre-silicon test readiness, ensuring DFX features, test patterns and ATE test programs are ready ahead of tapeout and silicon arrival
•Lead post-silicon DFX bring-up execution, coordinating SCAN, MBIST, IO and other test content debug across DFX, validation and test engineering teams
•Track and drive productization milestones partnering with Operations, including ATE test time reduction, test coverage, yield learning and DPPM/quality targets required for qualification and production release
•Coordinate handoffs to Operations and support production ramp readiness, including system-level and datacenter test needs
•Run regular program execution reviews, capture decisions, actions and owners, manage scope changes, and drive items to closure
•Proactively identify schedule and quality risks, partner with engineering on mitigation plans, and provide clear, data-driven status and recommendations to leadership for trade-off decisions
•Assemble lessons learned and apply standard methodologies from one program to another to continuously improve DFX execution
What we need to see:
•BS (Masters preferred) in Electrical Engineering, Computer Engineering or a related field or equivalent experience
•6+ years of experience in semiconductor technical program management, test engineering, DFX or post-silicon validation
•Hands-on knowledge of the ASIC/SoC development flow, with working familiarity with DFX concepts (SCAN, ATPG, MBIST, JTAG) and post-silicon bring-up, test and productization
•Demonstrated ability to drive execution with multi-functional teams and concurrent programs while keeping sophisticated schedules on track
•Understands and deals well with rapid development cycles and constant change; remains flexible and calm in the face of uncertainty
•Self-motivated and proactive with strong attention to detail and demonstrated critical thinking capabilities
•Proficient with program management tools and data (e.g., Jira, Smartsheet, Confluence); scripting experience in Python is a plus
Ways to stand out from the crowd:
•Experience with ATE platforms and production test flows
•Exposure to datacenter testability challenges, including system-level and in-field test.
•Experience with yield analysis and manufacturing quality metrics.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 258,750 USD for Level 4, and 200,000 USD - 322,000 USD for Level 5. You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 1, 2026. This posting is for an existing vacancy.
