NVIDIA is seeking a Physical Design and Timing Engineer to join our silicon implementation team. This role focuses on timing analysis, timing closure, and signoff quality across complex ASIC and SoC designs. You will work closely with physical design, front-end design, methodology, and CAD teams to drive robust implementation at advanced process nodes. This is a strong fit for an engineer who enjoys deep analysis, problem solving, and improving quality at block and full-chip levels.
What you'll be doing:
•Drive static timing analysis and timing closure for block and/or full-chip designs.
•Develop, review, and debug timing constraints, scenarios, and signoff checks.
•Analyze setup, hold, noise, and variation-related timing issues and drive closure with cross-functional teams.
•Partner with physical design engineers on floorplan, CTS, route, ECO, and convergence activities.
•Review reports, identify root causes of violations, and recommend high-quality fixes with minimal design impact.
•Improve timing methodology, automation, and debug efficiency using Tcl, Perl, and/or Python.
What we need to see:
•B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.
•5+ years of experience in ASIC or SoC physical design, timing analysis, or implementation.
•Strong understanding of static timing analysis fundamentals, timing constraints, and timing closure.
•Hands-on experience with industry-standard EDA tools such as PrimeTime, ICC2, Innovus, Tempus, or equivalent.
•Experience debugging setup/hold violations, clocking issues, and ECO impacts.
•Solid scripting skills in Tcl plus familiarity with Perl or Python.
•Good communication skills and ability to work across design, CAD, and verification teams.
Ways to stand out from the crowd:
•Experience with advanced-node implementation and signoff.
•Knowledge of MMMC flows, SI, OCV/AOCV/POCV, and power-aware timing analysis.
•Experience improving timing methodology or developing reusable automation.
