About the Role
We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for contributing to our latest generation chiplet interface projects.
What you'll be doing:
•Performing physical layout for mixed-signal functions like top level, high speed datapaths and high-speed clocking designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.
•You'll work closely with mixed-signal design engineers to customize designs for integration in VLSI products.
•Take part in floor planning, custom layout and verifying against design rules and schematics.
What we need to see:
•Have a BSEE or equivalent experience. Minimum of 5+ years industry experience in Mask and Layout Design.
•Working independently on creating layout with excellent quality.
•Deep understanding and previous experience for FinFET technology is a must.
•You are an authority with Cadence custom circuit design tools - particularly virtuoso.
•Able to handle fast-paced project and iterate quickly based on designer's feedback.
•You can work effectively in a team, good interpersonal skills, enthusiasm, and positive energy.
•Scripting languages like perl, python, skill etc. is a plus.
•Should have knowledge of DRC and LVS checking flows, ability to customize decks.
