NVIDIA

Senior Digital Design Engineer

In short

NVIDIA's Semi-Custom Silicon products group is hiring a Senior Digital Design Engineer to craft and implement RTL blocks for NVLink Fusion-based AI infrastructure System-on-Chips. The role covers micro-architecture specification, RTL implementation, verification closure, and collaboration with chip architects and SoC integration engineers. Requires 12+ years of experience, a degree in Electrical or Computer Engineering, deep ASIC design flow knowledge, and experience with high-speed connectivity protocols like NVLink, PCIe, Ethernet, or UCIE. Based in Santa Clara, CA, with base salary ranging from $196,000 to $368,000 depending on level.

We are looking for a Digital Design Engineer to join our Semi-Custom Silicon products group. In this role, you will join a group of hard working engineers crafting and implementing NVLink Fusion based AI infrastructure System-on-Chips. You will get a chance to create real impact in a dynamic, industry leading, technology-focused company, while working on NVLink Fusion technology. NVLink Fusion is the enabler for the next generation of standardized rack-scale AI connectivity.
What you'll be doing:
•As a key member of the NVLink Fusion design team, you will analyze the architectural requirements, perform the trade-off analysis for implementation, and deliver high performance, area and power efficient RTL Blocks.
•Craft micro-architecture specification, implement in high-quality RTL, and deliver a fully verified, synthesis and timing clean block.
•Collaborate with chip architects, verification engineers, formal verification engineers, and SoC integration engineers in order to meet the goals of the block in a timely manner.
•Identify potential IP solutions for specific use cases and assist in selecting, customizing and integrating the right IP solutions.
What we need to see:
•Bachelors or Master's Degree, or equivalent experience in Electrical Engineering or Computer Engineering.
•12+ years of relevant work experience.
•Experience working with high-speed connectivity protocols such as NVLink, PCI-Express, Ethernet, UCIE etc.
•Proven track record of delivering high bandwidth datapath blocks such as data movers, protocol adaptors, network-on-chip, arbiters and schedulers etc.
•Deep understanding of ASIC design flows and methodology.
•Strong analytical and interpersonal skills, excellent teammate.
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 196,000 USD – 310,500 USD for Level 5; and 232,000 USD – 368,000 USD for Level 6. You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 7, 2026. This posting is for an existing vacancy.
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