About the Role
NVIDIA is looking for a motivated DFT-Timing Engineer to join a dynamic and growing team.
What you'll be doing:
•Drive timing analysis and closure for DFT logic on all Nvidia chips (GPUs/CPUs/DPUs/LPUs/SoCs) at all hierarchical levels (block/cluster/full-chip).
•Work with PD, DFX, Clocks and other teams to come up with timing closure strategy, develop timing constraints for custom DFT designs, drive timing and power convergence, and implement ECOs.
•Continuously improve workflows and designs by introducing more automation, resilience, and standardization.
What we need to see:
•BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years' experience or MS (or equivalent experience) with 2+ years' experience.
•Hands-on experience in Static Timing Analysis (STA) and driving timing convergence at full-chip/sub-chip level in advanced technology nodes.
•Expertise in analysis and fixing of timing paths through ECOs.
•Expertise in developing timing constraints.
•In-depth knowledge of industry standard timing convergence tools.
Ways to stand out from the crowd:
•Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, iJTAG, etc.
•Background in domain specific STA and timing convergence, such as Serdes, Processor, IO, SMVA, etc.
•Experience in methodology and/or workflow development.
Compensation
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 136,000 USD – 218,500 USD for Level 3; and 168,000 USD – 264,500 USD for Level 4. You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until November 6, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.
