About the Role
As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. Successful candidates will be joining a vibrant team with a proven track-record of success over 30-years of evolution and revolution in the advancement of high-speed circuits used in broadband fiber-optic modems. This team pioneered the introduction of the world's first high-speed DAC and ADC analog macros that ushered in the era of coherent fiber-optic product solutions.
To further strengthen the team, Ciena is looking for a hardworking analog layout engineer who will be working on advanced high-speed analog design circuits in the latest deep-submicron CMOS and/or BiCMOS technologies. The role involves driving and implementing best-in-class high-speed analog layouts that extract the highest performance from the world's most advanced CMOS and BiCMOS technologies. These analog macros include electrical interface-facing DAC and ADC based SERDES solutions for 112G and 224G, optical-line-facing high-speed DAC and ADC circuits interfacing with optical modulators and detectors, transimpedance amplifiers, modulator driver circuits, and critical precision analog circuits for control and monitoring functions, etc.
Responsibilities
•Develop block and macro level layouts including floor-planning, placement, routing and optimization.
•Carry out layout feasibility studies on various circuit designs in collaboration with senior analog designers, finding the best possible solution considering various trade-offs and discussions with team members.
•Write automation scripts for layout flow improvements including pcells.
•Conduct thorough verification checks such as DRC, ANT, LVS, PERC, EM, IR to ensure the final layout possesses the highest level of quality.
•Debug ESD violations reported by PERC and suggest solutions.
•Investigate new features within the layout tools and processes used for creating layouts with the aim of enhancing productivity.
•Mentor junior layout team members as applicable who may assist with some aspects of the overall layout implementation.
•Provide regular status updates, participate in team meetings and share experiences with the rest of the group.
Requirements
•Bachelor's or higher degree in Electrical Engineering or related field, with 5+ years of relevant industry experience.
•Experience in custom analog and mixed signal layout design with a strong knowledge of deep sub-micron CMOS devices (e.g. Finfet transistors).
•Highly motivated with strong team player skills, exhibits a positive can-do attitude and ability to seamlessly integrate into an existing team culture.
•Strong communication and interpersonal skills to collaborate with cross-functional teams.
•Experience in custom layout design of Analog/Mixed Signal designs (e.g. ADC, DAC, PLL, SERDES …).
•Proficiency in using industry-standard layout tools (e.g., Cadence Virtuoso, Siemens Calibre, Ansys Totem …) and familiarity with layout design flows for advanced technology nodes.
•Strong analytical and problem-solving skills to identify and address layout-related issues efficiently.
•Proficient in layout techniques for Floor Planning, device matching, minimizing parasitics, RF shielding, EM, IR drop, ESD and high-frequency routing.
•Meticulous attention to details, ensuring the highest level of accuracy and quality in all layout designs.
•Familiarity with semiconductor manufacturing processes and foundry technologies.
•Ability to thrive in a fast-paced, dynamic work environment and adapt quickly to changing project requirements.
•Solid understanding of RC delay, electromigration, and coupling effects.
•Familiarity with guard rings, DNW, PN junctions, advanced process effects such as LOD, OSE, WPE etc.
•High level of proficiency in interpreting DRC, PERC, ANT, PAD, ERC and LVS.
•Ability to identify failure-prone circuit and layout structures and proactively work with circuit designers to resolve problems.
•Scripting skills in PERL or SKILL are a plus, but not required.
•A history of successful analog circuit product deliveries.
Pay and Status
•Pay Range: annual salary range $141,700 - $226,300 CAD.
•Vacancy Status: Future Opportunity.
•Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting diverse products, industries, and lines of business. The pay range information provided pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
•Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission.
•Benefits include medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time.
