About the Role
With the continuous improvement of chip technology, design scale and performance/power ratio, the physical design of digital chips is facing outstanding challenges in high frequency, low power consumption and multiple applications. High efficiency, high quality of the implementation of the construction chip is the guarantee of the company's competitiveness. As an ASIC-PD engineer at NVIDIA, you'll be responsible for the stage from RTL frozen to tape out, including synthesis, formal verification, constraints definition, timing closure/sign off, study on the timing impact of process and related methodology work. You will face the biggest challenge based on the most advanced process on building chips in the world.
What You'll Be Doing
•Chip integration and netlist generation
•Synthesis, RTL/netlist quality check and formal verification
•Constraints creation and validation, timing budget
•Work with ASIC team to analyze/resolve special timing issues as well as cross-team collaboration to implement chip partitioning and floorplan
•Work in conjunction with PR engineers to achieve timing closure for both partition and full chip level
•Achieve special mode timing closure, such as io, test, clock, async etc.
•Function eco creation
•Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout)
•Flow automation development for above areas
•Methodology in any of above areas
What We Need to See
•MS in EE or Microelectronics
•Project experience in IC design implementation
•Courses taken in circuit design, digital design
•Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is helpful
•Proficient user of Python or TCL is helpful
•Proficient in English reading and writing
