About the Role
The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. This role offers the opportunity to contribute to the front-end implementation of industry leading ASIC technology. As ASIC FrontEnd Implementation Engineer, you will be responsible for the synthesis, static timing analysis, and DFT implementation of assigned IP sub-systems.
How you will make an impact
•Execute frontend implementation for assigned IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation
•Develop and maintain timing constraints to support synthesis and signoff for subsystem integration
•Validate clock domain crossings for top-level ASIC integration to ensure functional integrity
•Insert scan test, MBIST and other test features at both RTL and netlist levels
•Work with design engineers to improve RTL for test coverage
•Execute Automatic Test Pattern Generation (ATPG) and conduct pattern re-simulation and gate level simulation
•Implement boundary scan IEEE1149.1 and other standards
•Create and optimize scripts, tools, and documentation that improve synthesis, static timing and DFT workflows
•Collaborate closely with ASIC integration, IP development, physical design, and external Electronic Design Automation (EDA) partners to align frontend and backend implementation activities
The must haves
•B.Sc. in Electrical Engineering, Computer Engineering with 5+ years of industry experience in ASIC digital design and Design for Test (DFT)
•Proven DFT experience including insertion, vector optimisation and DFT timing analysis using tools from one of the major EDA vendors
•Proven experience in implementing and debugging digital DFT simulations
•Industry experience using synthesis and/or static timing analysis tools within an ASIC development environment
•Knowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation
•Familiarity with RTL design principles and hardware description languages
•Ability to work effectively within multidisciplinary engineering teams and manage deliverables to project schedules
Nice to haves
•Experience with additional backend implementation activities such as floor-planning and place and route
•Hands on exposure to deep submicron ASIC technologies and advanced timing closure methodologies
•Background supporting DSP centric or highspeed ASIC development programs
•Experience working with external EDA vendors or foundry technology teams
Compensation & Benefits
Salary Range: The salary range for this role in Ottawa is $111,900 - $178,700.
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. The pay range information provided pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time.
